Traceable and verifiable flow control using combinatorial optimization limit. Mining FSM, optimize and debug the user control Mapping software customized for each FPGA device ensures optimum performanceĪs a result, automatic memory and DSP projects with a desirable area, provides strength and quality of the results. Manage multiple design implementations for major projects team Regional optimal results when using the FPGA of Achronix, Altera, Lattice, Microsemi, Xilinx TCL scripting for automation and combining the adjustable support, debugging and reporting The running time of acceleration with support for up to 4 processors Synplify software uses an easy interface and ability to combine incremental and visual analysis is HDL code.įeatures and amenities Synopsys Synplify:Īutomatically compile points flow increased by 4 times faster The software also supports FPGA architecture by a variety of FPGA vendors including Altera, Achronix, Lattice, Microsemi and Xilinx support. Synplify Pro VHDL and Verilog language constructs of the latest software, including SystemVerilog and VHDL-2008 support. Synopsys Synplify FPGA design software, the industry standard for high-performance and cost-effective.
Working with Synopsys Synplify with Design Planner L-2016.03-SP1 full
Which matches the sort of thing you're seeing.Īnd I can't see how to change the resolution anywhere.Download Synopsys Synplify with Design Planner L-2016.03-SP1 full license Link download Synopsys Synplify with Design Planner L-2016.03-SP1 full crack However, when trying a testcase based on said code it CD720 :"C:\Synopsys\fpga_I-2014.03-SP1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to nsĪnd a very simple testcase fails this assertion: assert 1 ns = 1000 ps severity failure Physical time types allow selection of a wide number range Range from –2147483647 to +2147483647 with units ranging fromįemtoseconds, and secondary units ranging up to an hour.
The support of predefined physical time types includes the expanded
The reference manual for my version of Synplify Pro (I-2014.03-SP1) has this statement in it:
(Arguably this is not an answer, more a "confirmation of the question" using the full version of the tool). So, how do I change this to 1ps or 1 fs for more accurate calculations involving time? I can't find any such information in the obvious sources. So the correct period (31.25 ns) is being rounded down to 31 ns, resulting in incorrect calculation of the delay counter load value.īut the implication is that Synplify (specifically, Actel Edition from MicroSemi Libero 9.1) uses 1ns resolution as its default for time unit resolution. Time: 128 ns Iteration: 0 Instance: /testbench/uut/uutĪnd 32MHz divided by 32258 does indeed give the 992Hz signal I was observing.Ĭhanging Modelsim's time resolution from its default (presumably 1ns) to 1ps, gives the expected result. Which reports (in simulation) as follows:Īt 125 ns: Note: Delay 32000 (/testbench/UUT/UUT/). Report "Delay " & DelayType'image(Period) severity NOTE Subtype DelayType is natural range 0 to Clock_Frequency Ĭonstant Period : DelayType := 1 ms / Clock_Period The crux of the code is this: constant Clock_Frequency : natural := 32_000_000 Ĭonstant Clock_Period : time := 1 sec / Clock_Frequency Simulating the behavioural model of this counter, I can see either correct or incorrect behaviour with no source code changes whatsoever. Not a difficult task, so you can imagine my surprise when the result runs at 992Hz. I am generating a 1khz pulse from a 32MHz clock, naturally via a counter.